Faster Complex SoC Design by Virtual Prototyping

Development of complex System on Chip (SoC) for modern communication systems has become more and more challenging. A designer has to bridge the gap between the requirements of the system at algorithmic level and its cycle true hardware description; the latter being synthesized for an Application Specific Integrated Circuit. This development requires numerous sub-steps, i.e., several intermediate descriptions on different abstraction levels of the same system. One of those levels can be an architecture level description implemented purely in software in form of a Virtual Prototype. This paper shows how Virtual Prototyping has been integrated in a design flow by a consistent design methodology and what advantages in terms of design efficiency have been gained.